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Forward references in Verilog

Verilog supports forward references in an odd/different manner.

If you instantiate a module with port connected to a signal line that
you have not declared, Verilog will instantiate a one-bit wire for you.
(and not complain during compile time). This is also true for wrongly
spelled wire names.

If you later attempt to declare the same wire, verilog will complain of
double-declarations.

You can get around this by declaring at the top line of every file
`default_nettype none . This will force verilog to flag all undeclared
wires.

see this thread for more information on this:
http://newsgroups.derkeiler.com/Archive/Comp/comp.lang.verilog/2009-01/msg00023.html

Part select in Verilog

Verilog allows you to declare the ranges of wires of components in
either increasing or decreasing order (0:n] or [n:0].

However, all references in a given system have to follow that same order
- regardless of whether it is a part-select, non-indexed assignment(s) etc.

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